Analog-to-digital conversion (ADC) is often used to sample analog signals so that such signals may be digitally represented. The need for digital representation of analog signals arises in a variety of applications such as digital communication receivers.
A variety of techniques to perform ADC are well known in the art. Two common techniques include the successive approximation (SA) ADC and the flash ADC. An SA ADC circuit generally produces a digital representation by processing an input analog signal through successive stages, each stage comprising a comparator configured to get a successively more accurate digital representation of the input analog signal. In a typical flash ADC circuit, an input analog signal value is compared with various reference levels, all at once, using multiple comparators. All other things being equal, because a flash ADC circuit has a single stage of comparators instead of multiple stages of comparators as in an SA ADC circuit, a flash ADC circuit may typically produce a digital representation of an analog input signal with lower latency than an SA ADC circuit. Therefore, the flash ADC technique is generally considered more suitable for a high speed application.
With the increasing demand for high data rates and constellation densities, especially in signals transmitted in the Giga Hertz (GHz) range, the demand for fast, accurate high speed ADC is ever increasing. When using a flash ADC circuit, this in turn may require certain aspects of the flash ADC circuit, such as suppressing errors in a digital representation of analog signals (sometimes called “bubble errors”), to be implemented using an accurate, high speed circuit.
In certain aspects of the disclosure, a better error filtering circuit is needed to meet the increased speed and accuracy requirements.